Central Processing Unit (CPU)

    AQA
    GCSE

    The Central Processing Unit (CPU) functions as the primary component for instruction execution based on the Von Neumann architecture. It operates via the Fetch-Decode-Execute cycle, coordinating the Control Unit (CU), Arithmetic Logic Unit (ALU), and registers to process data. System performance is quantitatively defined by clock speed, cache size, and core count, necessitating an understanding of how these factors mitigate bottlenecks. Mastery requires distinguishing between the roles of specific registers such as the MAR, MDR, and Program Counter during instruction processing.

    0
    Objectives
    3
    Exam Tips
    4
    Pitfalls
    4
    Key Terms
    5
    Mark Points

    What You Need to Demonstrate

    Key skills and knowledge for this topic

    • Award 1 mark for stating the Control Unit sends control signals to direct data flow around the CPU
    • Award 1 mark for identifying that the Program Counter (PC) holds the address of the *next* instruction to be fetched
    • Credit responses that describe the Fetch stage: address copied from PC to MAR, data fetched to MDR, PC incremented
    • Award 1 mark for explaining that cache memory improves performance by providing faster access to frequently used instructions than RAM
    • Award 1 mark for linking multiple cores to the ability to execute multiple instructions simultaneously (parallel processing)

    Marking Points

    Key points examiners look for in your answers

    • Award 1 mark for stating the Control Unit sends control signals to direct data flow around the CPU
    • Award 1 mark for identifying that the Program Counter (PC) holds the address of the *next* instruction to be fetched
    • Credit responses that describe the Fetch stage: address copied from PC to MAR, data fetched to MDR, PC incremented
    • Award 1 mark for explaining that cache memory improves performance by providing faster access to frequently used instructions than RAM
    • Award 1 mark for linking multiple cores to the ability to execute multiple instructions simultaneously (parallel processing)

    Examiner Tips

    Expert advice for maximising your marks

    • 💡When describing the Fetch-Execute cycle, explicitly mention the transfer of data between specific registers (e.g., 'PC to MAR') rather than just saying 'data moves'.
    • 💡For performance questions, distinguish between 'Clock Speed' (cycles per second) and 'Core Count' (independent processing units).
    • 💡Memorise the full names of registers; using acronyms (MAR, MDR) is acceptable only if you are precise with their distinct functions.

    Common Mistakes

    Pitfalls to avoid in your exam answers

    • Stating the Program Counter holds the *current* instruction's address rather than the *next* one
    • Confusing the Memory Address Register (MAR) with the Memory Data Register (MDR) when describing data transfer
    • Asserting that doubling the number of cores automatically doubles processing speed, ignoring software optimization or sequential task limitations
    • Describing the CPU as 'thinking' or using anthropomorphic language instead of 'processing' or 'executing'

    Key Terminology

    Essential terms to know

    Likely Command Words

    How questions on this topic are typically asked

    State
    Describe
    Explain
    Compare
    Complete

    Ready to test yourself?

    Practice questions tailored to this topic